1. Field of the Invention
This invention relates to integrated circuit testing and repair, and more particularly to the repair of embedded memory devices.
2. Description of the Related Art
Advances in integrated circuit fabrication technology continue to enhance the ability to form increasingly more circuitry upon integrated circuit chips. As the complexity of circuitry formed upon chips increases, the complexity of the testing required to ensure the circuitry functions correctly also increases. However, conventional testing using external test equipment is made extremely difficult as much of the circuitry formed on integrated circuit chips is typically not controllable or observable from input/output (I/O) pads. This is especially true of memory arrays formed along with random logic circuitry upon integrated circuit chips (i.e., embedded memory arrays). A solution to the chip testing problem increasingly being adopted is to incorporate testing circuitry along with the operational circuitry upon the integrated circuit chips themselves. Built-in self-test (BIST) circuitry is one example of such testing circuitry. Array BIST (ABIST) circuitry is commonly used to test proper operation of embedded memory arrays.
In addition to the above, increasing size, density and complexity in memory technologies lead to higher defect density and a corresponding decrease in yield. One technique for dealing with such defects involves built-in self-repair (BISR). Generally speaking, BISR consists of replacing defective memory columns with spare columns. BISR may be implemented at the column, row, block or bit level. Memory cells of memory arrays are typically arranged in orthogonal rows and columns. Memory arrays are typically fabricated with redundant rows and/or columns to enable repairs on the array subsequent to fabrication. Rows and/or columns of the memory array which do not function correctly may be identified and replaced by the redundant rows and/or columns subsequent to fabrication. Replacement mechanisms include current-blown fuses and laser-blown fuses. Such fuses may be selectively blown in order to deselect a failing portion of the array and select a redundant portion to replace the failed portion. However, directly associating fuses with repair elements on a CPU die with many arrays may be inefficient as it is likely that only a few repairs may need to be done. If many repairs need to be done to the arrays, it is likely that there would be a defect in the logic as well and the die may be unsalvageable in any event.
Accordingly, an efficient method and mechanism for performing repairs is desired.